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preliminary this document contains in f o r mation on a product under d e v elopment at ad v anced micro d e vice s . the in f o r mation is intended to help y ou e v aluate this product . amd rese r v es the r ight to change or discontinue wo r k on this proposed product without notic e . pu b lication# 17305 r e v : b amendment/ 0 issue date : m a y 1994 1 am79c987 ha r d ware implemented management in f ormation base (himib) d e vice distinctive char a cteristics n p ro vides repeater management functions , comp l ying with all options detailed in the l a yer management f or 10 m b yte/s baseband repeate r s (ieee 802.3k) standa r d n ful l y compatible with the n o vell hub management interface (hmi) speci?ation n p ro vides additional ieee m a u management functions (802.3p draft) n interfaces direct l y with amd s am79c981 integrated multipo r t repeater plus (imr+) d e vice to b uild a ful l y managed repeater n multiple himib/imr+ d e vices can be used in a system n 8-bit mic r op r ocessor interface all o ws attri b ute access , interrupt cont r ol , and management cont r ol n maskable interrupts f or noti?ation of status/ er r or repo r ting n interna l ?eceive on l y m a c tra c ks all address in f ormation and monito r s e xception conditions n suppo r ts mapping of node sou r ce addresses to po r t numbe r s , th r ough implementing sou r ce address match function n full 32-bit ha r d ware-implemented counte r s incur no additional software o verhead to keep net w ork statistics n pinout all o ws simple boa r d l a y out between imr+ and himib d e vices n 28-pin plcc d e vice in cmos technology f or l o w p o wer with a single + 5 v supp l y general description the am79c987 hard w are implemented management in f o r mation base (himib) d e vice is a highly integrated chip that simpli?s b uilding fully managed multipo r t re- peater s . the d e vice integrates all the necessa r y counter s , att r i b ute s , action s , and noti?ations speci?d b y the l a y er management f or 10 m b yte/s baseband repeaters (ieee 802.3k) standard, as w ell as addi- tional f eatures and enhancement s , including functions speci? to 10base-t repeater s . the himib chip is designed to be used in conjunction with amd s integrated multipo r t repeater plus (imr+) d e vic e . when connected to an imr+ (am79c981) d e vic e , the himib chip pr o vides complete repeater and per-po r t statistics on demand from an 8-bit parallel in- ter f ac e . no e xte r nal processor is required to k eep tra c k of att r i b utes locall y , as full 32-bit counters are pr o vided. the himib d e vice implements a simple 8-bit micropro- cessor inter f ac e , all o wing multiple himib d e vices to be used in a system . no additional logic is required f or in- ter f acing the himib d e vice to the imr+ d e vic e . the himib chip is pa c kaged in a 28-pin plastic leaded chip car r ier (plcc) . the d e vice is f ab r icated in cmos technology and requires a single + 5 v suppl y .
amd p r e l i m i n a r y 2 am79c987 block diagram attributes ck 802.3 receive mac imr+ management port interface rst d7C0 cs c/ d rd wr rdy int data port number status sclk si so col ack jam dat crs str bus interface 17305b-1 clock/ reset related amd products part no. description am79c98 twisted-pair ethernet transceiver (tpex) am79c100 twisted-pair ethernet transceiver plus (tpex+) am79c90 cmos local area network controller for ethernet (c-lance) am79c940 media access controller for ethernet (mace tm ) am79c900 integrated local area communications controller tm (ilacc tm ) am79c960 pcnet-isa single-chip ethernet controller (for isa bus) am79c961 pcnet-isa + single-chip ethernet controller (with microsoft plug n play support) am79c965 pcnet-32 single-chip 32-bit ethernet controller (for 486 and vl buses) am79c970 pcnet-pci single-chip ethernet controller for pci local bus am79c974 pcnet-scsi combination ethernet and scsi controller for pci systems am79c981 integrated multiport repeater plus tm (imr+ tm ) am7990 local area network controller for ethernet (lance) am7996 ieee 802.3/ethernet/cheapernet tap transceiver
am79c987 3 preliminary connection di a gram plcc logic symbol 1 2 3 4 2 8 2 7 26 2 5 5 24 23 22 21 20 19 1 8 1 7 1 6 15 6 7 8 9 10 11 1 2 1 3 14 sclk si crs str so cs rd d0 d1 d2 d3 v ss d4 d5 d6 d7 rdy v ss wr c/ d int v dd ack ck rst col jam dat am79c987 17305 b -2 d7? cs c/ d rd wr r d y int rst ck crs str sclk si so d a t j am a ck col v ss v ss v dd am79c987 17305 b -3
4 am79c987 preliminary ordering inform a tion standa r d p r oducts amd standard products are a v aila b le in s e v e r al pa c kages and operating r ange s . the order number ( v alid combination) is f o r med b y a combination of the elements bel o w . v alid combinations v alid combinations list congurations planned to be sup- po r ted in v olume f or this d e vic e . consult the local amd sales of ce to con r m a v ailability of specic v alid combinations and to che c k on n e wly released combination s . am79c987 j c device number/description am79c987 hardware implemented management information base (himib) optional p r ocessing blan k = standard processing b = burn- in oper a ting conditions c = commercial ( 0 c to +7 0 c) p a ck a g e type j = 28- pin plastic leaded chip carrier (pl 028) speed see product selector guide an d v alid combination v alid combinations am79c987 jc
am79c987 5 preliminary pin description ck clo c k input ck is the master 20 mhz clo c k . the imr+ d e vice x 1 pin m ust also be clo ck ed with the identical clo c k signal. rst reset input , active l o w dr iving this pin l o w resets the inte r nal logic of the himi b . the himib d e vice m ust be reset with the identi- cal synchronous rst signal of the imr+ d e vic e . note: none of the 32-bit and 48-bit attributes are cleared upon reset. si serial input (to the imr+ chip) output the si pin is used to output management po r t commands to the imr+ d e vic e . this pin should be con- necte d to the si pin of the imr+ chi p . so serial output (f r om the imr+ c hip) input the so pin is used to recei v e management po r t in f or- mation from the imr+ d e vic e . this pin should be connected to the so pin of the imr+ chi p . sclk serial clo c k output 10 mhz clo c k used to d r i v e the imr+ management po r t se r ial clo c k (sclk). crs carrier sense input the crs pin should be connected to the crs pin of the imr+ d e vic e . states of the inte r nal car r ier sense signals of the imr+ a ui and twisted-pair po r ts are se- r ially input on this pin continuousl y . str store output , high impedance this pin should be connected to the str pin of the imr+ chi p . this pin is an output when the himib d e vice is inter f aced to an imr+ d e vice ; otherwise it remains in high-impedance stat e . a ck a c kn o wledge input , active l o w when this input is asse r ted, it indicates that data on the d a t and j am inputs are v alid. col expansion collision input , active l o w when this input is asse r ted, it indicates that there is a tr ansmit collision because more than one imr+ d e vice is acti v e (requesting access to the e xpansion po r t). d a t expansion p o r t data input whe n a ck is asse r ted and j am is l o w , the e xpansion po r t data consists of the nrz recei v ed data . when a ck is not asse r ted, the state of d a t is ignored. j am jam input whe n a ck is asse r ted and j am is high, an acti v e imr+ d e vice is in a collision state . when j am is as- se r ted, the state of d a t will indicate either a multipo r t ( d a t = 0) or single-po r t ( d a t = 1) collision condition. whe n a ck is not asse r ted, the state of j am is ignored. d7? data input/output , 3- state data input/output pin s . these pins are in high- impedance state if the himib d e vice is not selected . c/ d command/data input this input pin all o ws selection of either the command or data po r t in the himib d e vic e . when this signal is high, the command po r t is selected and, when it is l o w , the data po r t is selected . this pin is typically con- nected to the least signicant bit of the address b u s . wr write st r obe input , active l o w when this pin is asse r ted and the cs is acti v e , a w r ite ope r ation is initiated . rd read st r obe input , active l o w when this pin is asse r ted and the cs is acti v e , a read ope r ation is initiated.
6 am79c987 preliminary cs chip select input , active l o w the chip-select input, when asse r ted, ena b les a read from or a write to the 8-bit parallel po r t of the himib d e vic e . r d y rea d y output , open drain ready is d r i v en l o w at the sta r t of e v e r y read or w r ite cycle and is released when the himib d e vice is ready to complete the transaction. int interrupt output , active l o w , open drain interr upt is d r i v en l o w when a n y of the unmas k ed ( ena b led) inter r upts occu r . v dd p o wer this pin supplies + 5 v to the d e vic e . connect to d v dd of the imr+ d e vic e . v ss g r ound these t w o pins are the 0 v re f erence f or the d e vic e . connect to d v ss of the imr+ d e vic e .
amd p r e l i m i n a r y 7 am79c987 functional description overview the functional specification of the himib device is a su- perset of that defined by the layer management for 1 0 mbyte/s baseband repeaters standard (ieee802.3k), commonly referred to as the repeater management standard. the himib chip contains the complete set of repeater and port functions as defined in the standard. all mandatory and optional capabilities are supported. these are defined as the basic control, performance monitor and address tracking capabili- ties. in addition, node address mapping and mau man- agement specific functions are implemented. the himib device keeps track of the ieee 802.3k speci- fied attributes by extracting data from the expansion port, management port, and port activity monitor (pam) port of the imr+ device. all attribute counts are held in 32 bit registers, as specified in the repeater manage- ment standard. for more detailed information, refer to the ieee 802.3 layer management for 10 mbyte/s baseband repeaters standard and amds ieee 802.3 repeater technical manual (pid #17314a). the himib chip supports the following repeater man- agement functions: repeater attributes: transmit collisions C 32-bit counter total octets C 32-bit counter port attributes: auto partition state C from imr+ chip readable frames C 32-bit counter readable octets C 32-bit counter frame check sequence errors C 32-bit counter alignment errors C 32-bit counter frames too long C 32-bit counter short events C 32-bit counter runts C 32-bit counter collisions C 32-bit counter late events C 32-bit counter very long events C 32-bit counter data rate mismatches C 32-bit counter auto partitions C 32-bit counter source address changes C 32-bit counter last source address C 48-bit register node id to port address map: source address match register (48-bit register) port actions: port admin control (enable / disable). note: the himib device executes this action by direct access to the imr+ device management port. individually maskable interrupts are available for the fol- lowing events: change in the port partitioning status change in the twisted pair ports link test state aui loop back error aui sqe test error source address changed source address match imr+ interface error the himib chip provides direct access to the manage- ment port of the imr+ device for additional functions in- cluding twisted pair port automatic receive polarity detection/correction state and enabling the alternate re- connection algorithm. the himib devices 8-bit microprocessor interface al- lows access to onboard registers. the interface is de- signed to be usable with a variety of available microprocessors and buses. the himib device can also be used to collect network statistics from a standard 802.3 mac device. this mode is programmed by setting the mac interface mode en- able bit in the configuration register. in this mode the himib device can be interfaced with any ethernet con- troller with a general purpose serial interface (gpsi). the himib device will record various network events oc- curring at that node of the network, and assign these gathered statistics to the aui port. all tp ports statistics are invalid in this mode.
amd p r e l i m i n a r y 8 am79c987 microprocessor interface access to the himib devices on-chip registers is made via its simple processor interface which is designed to be used by a variety of available microprocessors. the bus interface is designed to be asynchronous and can be easily adapted for different hardware interfaces. the interface protocol is as follows: asser t cs (low) and c/ d (high to access control and low to access data) asser t rd (low) to start a read cycle or wr (low) to start a write cycle the himib device forces rdy low in response to the falling edge of either of rd or wr note: cs is internally gated with rd and wr , such that cs may be permanently grounded, if not required. the start of read or write cycle is the time when cs and eithe r rd or wr strobes are both asserted (low). write cycle: data is to be placed on the data (d7C0) pins prior to rising edge of wr the himib device releases rdy (pulled high exter- nally), indicating that it is ready to latch the data wr strobe is de-asserted (high) in response to rdy. the himib chip latches data internally on ris- ing edge of wr the processor can stop driving the data pins after the rising edge of wr read cycle: the himib device drives the data (d7C0) pins the himib device releases rdy (pulled high exter- nally), indicating valid data rd strobe is de-asserted (high) in response to rdy. the external device should latch the himib chips data on the rising edge of rd . the himib device stops driving the data pins after the rising edge of rd typically, read and write cycles take 500 ns (10 ck clock cycles) to complete. upon reset, the interrupt pin ( int ) is not driven, all inter- nal sources of interrupts are cleared and all interrupts are disabled (masked). use of the int pin requires ex- plicit enabling by setting the appropriate enable bits. th e int pin is driven low when any of the enabled inter- rupts occur. th e int pin will go inactive after the internal source(s) of the interrupt are cleared by reading the corresponding status registers. register access all himib internal registers are accessed by reading or writing to or from two externally visible ports. these are the command port (c port) and the data port (d port). the c port is accessed by asserting c/ d pin high dur- ing read or write accesses. the d port is accessed by driving the c/ d pin low during read/write access to the himib device. as the c/ d pin is the only address line provided on the himib device bus interface, the internal register to be accessed must be selected by writing its address into the command port. the address appears to the programmer as two regis- ters referred to as the p and r registers, both of which are accessed via the command port. the p register se- lects the register port number (or bank number), and is accessed by writing a byte with the three most signifi- cant bits set to zero into the c port. the r register se- lects the register number (or attribute number), and is accessed by writing a byte with the three most signifi- cant bits set to one into the c port. once the c port is programmed with a valid port (bank) and register (attribute) number, the entire 32-bit attrib- ute is transferred to a holding register upon reading the first byte. subsequent accesses to the d port access the value in a least significant to most significant byte order. when reading, once the last byte is read, the attribute value is re-transferred to the holding register and the se- quence can be restarted. when the c port is programmed for access to these multi-byte registers, reading the d port causes the value of the register to be copied into the holding register. the data is then read out from the holding register. this se- quence is repeated until the last byte is read and the d port is accessed again. when the c port is (re)pro- grammed, the first byte read from the d port will be the least significant byte. note that the p and r registers can be accessed in any sequence prior to accessing the d port. if either p or r register is not written prior to accessing the d port then the previous value of p or r register will be used.
amd p r e l i m i n a r y 9 am79c987 port (p) register register (r) registe r command (c) port data (d) port c/ d = 1 bank 0 bank 1 register register 0 31 0 31 0 31 register bank 31 port (or bank) pointer register (or attribute) pointer 000xxxxx 111xxxxx c/ d = 0 17305b-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 1. overview of himib register definition an exception to the normal command/data port access scheme, is the status register which is read directly by reading only the c port. this allows the status register to be read directly, without the need to write to the c port. register definition in the following description, all bit fields are ordered such that the left most bit is the most significant bit. un- used port and register numbers are reserved and should not be accessed as this may cause device mal- function. when specifying the port or bank number, the following command byte is written to the c port: c port write msb lsb 0 0 0 p4 p3 p2 p1 p0 p[4:0] represent the register bank or port number. these are organized as follows: p = [p4p3p2p1p0] note that to access the p register the three most signifi- cant bits of this byte must be zero. p [4:0] port/registe r bank 0 repeater registers 1 port status registers 2 port control registers 1 6 C 23 twisted pair ports attributes 31 aui port attributes when specifying the register or attribute to be ac- cessed, the following command byte is written to the c port. c port write msb lsb 1 1 1 r4 r3 r2 r1 r0 r = [r4r3r2r1r0] note that to access the r register the three most signifi- cant bits of this byte must be one.
amd p r e l i m i n a r y 1 0 am79c987 for p = 0 (repeater registers), the following registers are accessible: r[4:0] register 10 source address match (6-byte) 12 total octets (4-byte) 13 transmit collisions (4-byte) 16 configuration register 28 version/device id 30 imr+ management port set register 31 imr+ management port get register register 12 and 13 are 4 bytes long and their contents are read in the least to most significant byte order. register 10 is 6 bytes long and can be read as well as written to in the least to most significant byte order. port status registers are organized as follows (p = 1): r[4:0] register 0 tp (twisted pair) ports partition status change 1 aui port partition status change 2 tp link status change 3 aui loop back error 4 reserved 5 aui sqe test error 6 tp source address change 7 aui source address change 8 tp source address match status 9 aui source address match status port control registers are organized as follows (p = 2): r[4:0] register 0 tp partition change interrupt enable 1 aui partition change interrupt enable 2 tp link status change interrupt enable 3 aui loop back error interrupt enable 4 reserved 5 aui sqe test error interrupt enable 6 tp source address change interrupt enable 7 aui source address change interrupt enable for other valid port numbers (p in the range 16...23 or 31), the following attribute registers are available: r[4:0] register 0 readable frames 1 readable octets 2 frame check sequence errors 3 alignment errors 4 frames too long 5 short events 6 runts 7 collisions 8 late events 9 very long events 10 data rate mismatches 11 auto partitions 12 source address changes 13 reserved 14 last source address registers 0 through 12 are 4 bytes long and their con- tents are read in the least to most significant byte order. register 14 is 6 bytes long and can be read as well as written to in the least to most significant byte order. note that the contents of all attribute registers are main- tained during an external reset. at power up, the values of all 4- and 6-byte attributes are random.
amd p r e l i m i n a r y 11 am79c987 table 1. summary of all the himib device registers register bytes access status register note: read the c port for status 1 r no need to specify the port or register number port/register bank p[4:0] register r[4:0] bytes access repeater registers 0 source address match 10 6 r/w total octets 12 4 r transmit collisions 13 4 r configuration register 16 1 r/w version/device id 28 1 r imr+ management port set register 30 1 w imr+ management port get register 31 1 r/w port status registers 1 tp partition status change 0 1 r aui partition status change 1 1 r tp link status change 2 1 r aui loop back error 3 1 r reserved 4 aui sqe test error 5 1 r tp source address change 6 1 r aui source address change 7 1 r tp source address match status 8 1 r aui source address match status 9 1 r port control registers 2 tp partition change interrupt enable 0 1 r/w aui partition change interrupt enable 1 1 r/w tp link status change interrupt enable 2 1 r/w aui loop back error interrupt enable 3 1 r/w reserved 4 aui sqe test error interrupt enable 5 1 r/w tp source address change interrupt enabl e 6 1 r/w aui source address change interrupt enable 7 1 r/w attribute registers 16C23, 31 readable frames 0 4 r readable octets 1 4 r frame check sequence errors 2 4 r alignment errors 3 4 r frames too long 4 4 r short events 5 4 r runts 6 4 r collisions 7 4 r late events 8 4 r very long events 9 4 r data rate mismatches 10 4 r auto partitions 11 4 r source address changes 12 4 r reserved 13 last source address 14 6 r/w note that all register locations listed as reserved and those which might be accessed by values or combinations of p and r which are not listed in the table above should not be accessed by the software. read/write access to reserved registers may cause incorrect operation.
amd p r e l i m i n a r y 12 am79c987 detailed register functions status register the himib status register can be accessed at any time by reading the c port. the 8-bit quantity read has the following format: c port read msb lsb e i s x x x x x i interrupt. this bit reflects the state of the int output pin. if this bit is set to 1, then this himib device is driv- ing the int pin. note that the int pin is an open drain output and multiple devices may share the same in- terrupt signal. e interface error. this bit is set if the himib device is unable to communicate with the imr+ device. this bit is reset upon reading this register. s source address match. this bit is set if the interrupt is caused by a source address match of the incoming data packet. this bit remains set until the tp and/or aui source address match status register(s) in the port status registers are read. x reserved. the values of reserved bits are indeterminate. repeater, port status, port control and port attribute register access the bit pattern which must be written to the c port in or- der to correctly set the value of the r register to access each of the registers is described in this section. repeater register bank these registers are accessed by writing the bit pattern 0000 0000 to the c port, i.e., p[4:0] = 0. content of all attribute counters are indeterminate upon power up. source address match register p[4:0] = 0, r[4:0] = 10 byte 0 byte 1 byte 2 byte 3 byte 4 byte 5 bit 7 bit 47 bit 0 bit 40 msb lsb d port read/write this is a read/write register. the 6 bytes are read or writ- ten in low byte to high byte order. the sequence is (re)started once the c port is programmed for access to this register. this register may be used to track nodes within a lan by reporting the port that received a packet with a specific source address (sa). the source ad- dress field of an incoming packet is always compared with the 48-bit quantity stored in this register. the initial value of this register is indeterminate. a match is indicated by the himib device by setting the corresponding bit in the tp or aui source address match status register for the receiving port. if the corre- sponding source address match interrupt enable bit is enabled, then the int output pin is driven low. the set bit(s) in the tp/aui source address match status reg- isters are cleared when these registers are read. note that once a write sequence is started, all 6 bytes must be written in order to change the contents of this register. total octets p[4:0] = 0, r[4:0] = 12 byte 0 byte 1 byte 2 byte 3 bit 7 bit 31 bit 0 bit 24 msb lsb d port read this is a 4-byte attribute, read only register, whose con- tents are incremented while the repeater is repeating packet data. this counter is a truncated divide by 8 of the total number of bits transmitted by the repeater. the counter is incremented for non-collision packets with valid sfd (start of frame delimiter). this attribute in- crements by same amount for all himib devices con- nected to the same expansion bus in a repeater. the 4 bytes in this attribute are sequentially accessed by reading the d port, least significant byte first. note that once the c port is programmed for access to this at- tribute, reading the d port causes the value of this regis- ter to be copied to the internal holding register. the data is then read from the holding register, without affecting this attribute. this sequence is repeated when the last byte is read and the d port is accessed.
amd p r e l i m i n a r y 13 am79c987 transmit collisions p[4:0] = 0, r[4:0] = 13 byte 0 byte 1 byte 2 byte 3 bit 7 bit 31 bit 0 bit 24 msb lsb d port read transmit collisions is a 4-byte read-only attribute that counts the number of transmit collisions this repeater has detected. the value of the transmit collisions at- tribute is a 32-bit counter with a minimum rollover time of 15 hours. the 4 bytes in this attribute are sequentially accessed by reading the d port, least significant byte first. note that once the c port is programmed for access to this at- tribute, reading the d port causes the value of this regis- ter to be copied to the internal holding register. the data is then read from the holding register, without affecting this attribute. this sequence is repeated when the last byte is read and the d port is accessed. configuration register p[4:0] = 0, r[4:0] = 16 this is a read/write register. the value read is the same as that written. only zeros should be written into unused bits. all bits are cleared upon reset. d port read/write msb lsb e i s m 00 0 0 i enable interrupts. when this bit is set to 0, all inter- rupts from this himib device are masked (but not cleared) and the int output pin is forced to inactive state (not driven). e interface error interrupt enable. when this bit is set to 1, the himib device generates an interrupt if the imr+ interface is not functioning correctly. s source address match interrupt enable. when this bit is set, the himib chip will generate an interrupt if the source address of the received packet matches that programmed into the source address match register (in the repeater register bank). m mac interface mode enable. when this bit is set to 1, the himib device is assumed to be interfaced to an 802.3/ethernet mac controller. in this mode only statistics for port 31 (aui) are valid. the expansion port interface statistics are reported for port 31 (aui). the himib chip must be kept in this mode until an external reset occurs. when the himib chip is interfaced to a mac device, such as amds lance (am7990) and mace (am79c940) etc., the crs pin from the mac device should be connected to the crs pin of the himib chip. also, the so input pin of the himib chip should be tied high. note that in this mode, the himib chip will report an interface error in the status register since there is no connection to the management port. therefore, it is rec- ommended that the interface error interrupt is left dis- abled. certain attributes specific to the repeater management standard, such as bit rate error, aui loop- back error etc., will have no meaning. note: once this bit is set by software, it should not be cleared again as this may cause incorrect device operation. version and device id register p[4:0] = 0, r[4:0] = 28 this is a read only register. the 8-bit read has the follow- ing format: d port read msb lsb v 2 v3 v1 v0 d3 d2 d1 d0 v version. these bits contain the himib chip version code. software may interrogate these bits to deter- mine additional features that may be available with future versions of the device. the original version is 0000. d device id. the himib device detects the repeater version upon reset. this field is updated to report the type of physical repeater attached to the himib device. d device 0 imr chip (does not support all attributes) 1 imr+ chip 2C15 reserved for future use note: if the himib chip detects an interface error upon reset, then this field may not contain valid data. imr+ management port set register (s) p[4:0] = 0, r[4:0] = 30 d port write msb lsb d 6 d7 d5 d4 d3 d2 d1 d0 this is a write only register. this register is used for sending a set command to the imr+ device. when a byte is written to this register, the himib chip will serial- ize and transfer this byte to the imr+ management port.
amd p r e l i m i n a r y 14 am79c987 if a get command is written to this register accidentally, the imr+ device output will be retained in the get regis- ter, however, the management interface error bit will be set in the status register. writing to this register prior to execution (transfer) of the last command (get or set) causes the processor to be placed into the wait state. imr+ management port get register (g) p[4:0] = 0, r[4:0] = 31 d port read/write msb lsb d 6 d7 d5 d4 d3 d2 d1 d0 this is a read/write register. this register is used to transfer a get command to the imr+ device. this is per- formed by serializing and transferring the command placed into this register to the imr+ device following the end of the processor write cycle that writes the get com- mand. the byte returned by the imr+ chip is then placed in this register, overwriting its previous content. the microprocessor can read the byte result of the get operation once the information has been transferred to the himib device. if the read operation is started prior to completion of this transfer the himib device will hold the rdy line inactive until the transfer is complete. in most applications this will insert wait states into the processor read cycle. if a set command is written to this register accidentally, the imr+ device will receive the set command. how- ever, the management interface error bit will be set in the status register. note that reading the imr+ twisted pair bit rate error status registers using the get command may affect ac- curacy of the bit rate error attribute. port status registers these registers are accessed by writing the bit pattern 0000 0001 to the c port, i.e., p[4:0] = 1. these registers are read only and are cleared to 0 upon reading. tp and aui partition status change any port changing state from the partitioned to the re- connected state, or vice versa, causes the appropriate bit to be set to 1, in one of these two registers. tp ports p[4:0] = 1, r[4:0] = 0 the format for the tp ports is: d port read msb lsb t 6 t7 t5 t4 t3 t2 t1 t0 aui port p[4:0] = 1, r[4:0] = 1 for the aui port, only the most significant bit is used. bits denoted as x are undefined. d port read msb lsb x a x x x x x x tp link status change p[4:0] = 1, r[4:0] = 2 a change in the link test state of a tp port (from link fail to link pass or vice versa), causes the appropriate bit to be set to 1 in this register: d port read msb lsb t 6 t7 t5 t4 t3 t2 t1 t0 aui loop back error p[4:0] = 1, r[4:0] = 3 this register is not valid for the imr device (am79c980). when the himib chip is interfaced with the imr+ device (am79c981), the most significant bit (a) is set to 1 if the aui port is connected to a mau which does not loopback data from do to di during transmis- sion. for the error to be detected, the network needs to be active and a packet transmitted from the aui port. bits denoted as x are undefined. d port read msb lsb x a x x x x x x note that if the do to di loopback path is not opera- tional, this bit will be set again when the next packet is transmitted via the aui port.
amd p r e l i m i n a r y 15 am79c987 aui sqe test error p[4:0] = 1, r[4:0] = 5 this register is not valid for the imr device (am79c980). when the himib device is interfaced with the imr+ chip (am79c981), this bit is set to 1 if the aui port is connected to a mau with sqe test enabled. for the error to be detected, the network needs to be active and a packet transmitted from the aui port. bits denoted as x are undefined. d port read msb lsb x a x x x x x x note that if the error persists, once read, this bit will be set again when the next packet is transmitted via the aui port. tp and aui port source address change status a change in the source address of a valid received frame from any port causes the appropriate bit to be set in these registers. the source address assigned to any port after power up is indeterminate, and the first packet received from any port will cause the sa changed status bit for that port to be set. tp ports p[4:0] = 1, r[4:0] = 6 tp ports source address changed status: d port read msb lsb t 6 t7 t5 t4 t3 t2 t1 t0 aui port p[4:0] = 1, r[4:0] = 7 aui port source address changed status: d port read msb lsb x a x x x x x x note: the last source address attribute is program- mable and can be used to store the expected node id for this port. if the appropriate interrupt is also enabled, then a change in the source address can be used to alert the network manager of an unauthorized access. this is particularly useful for segments that are supposed to be connected to a single station. tp and aui port source address match status when the source address of the received packet from any port matches that programmed into the source ad- dress match register (in the repeater registers), then the appropriate bit will be set in the following registers: tp ports p[4:0] = 1, r[4:0] = 8 d port read msb lsb t 6 t7 t5 t4 t3 t2 t1 t0 aui port p[4:0] = 1, r[4:0] = 9 d port read msb lsb x a x x x x x x note: this function is useful for mapping an individual node id to a specific port on the repeater. port control registers these registers are accessed by writing the bit pattern 0000 0010 to the c port, i.e., p[4:0] = 2. all are read/write registers. a set (1) control bit enables an interrupt or function for the corresponding port. all control registers are cleared upon reset. tp and aui partition status change interrupt enable these two registers are used to enable or mask inter- rupts caused by a change in the port partitioning status. all interrupts are disabled and all status bits are cleared upon hardware reset. note that disabling an active inter- rupt source causes the int output to be placed into an inactive state. tp ports p[4:0] = 2, r[4:0] = 0 d port read/write msb lsb t 6 t7 t5 t4 t3 t2 t1 t0 aui port p[4:0] = 2, r[4:0] = 1 d port read/write msb lsb x a x x x x x x the aui port only uses the most significant bit (a) and all other bits are reserved. software should be designed to write 0s into unused bits.
amd p r e l i m i n a r y 16 am79c987 tp link state change interrupt enable p[4:0] = 2, r[4:0] = 2 setting any of the bits in this register causes the int pin to be driven when there is a change in the link test state of the corresponding tp port. the corresponding status bit in the tp link status change register is set t o 1. d port read/write msb lsb t 6 t7 t5 t4 t3 t2 t1 t0 aui loop back error interrupt enable p[4:0] = 2, r[4:0] = 3 setting the a bit to 1 in this register causes th e int pin to be driven when the imr+ chip senses a loop back error condition at the aui port. d port read/write msb lsb x a x x x x x x note that the himib device will continue generating in- terrupts every time a packet is transmitted by the aui port while this condition exists. this does not necessar- ily indicate a problem as an unconnected aui port will always report loop back error. aui sqe test error interrupt enable p[4:0] = 2, r[4:0] = 5 setting the a bit to 1 in this register causes th e int pin to be driven when the imr+ chip senses a sqe test error condition at the aui port (attached mau has sqe test enabled). note that the himib device will continue generating in- terrupts every time a packet is transmitted by the aui port, while this condition exists and this interrupt is enabled. d port read/write msb lsb x a x x x x x x tp and aui source address change interrupt enable these two registers are used to enable or mask inter- rupts caused by a change in the source address of a port. a tp port connected to another repeater or an aui connected to a mixing (multiple dtes) segment will have frequent source address changes. a tp port connected to a single end station will only de- tect a change of address if the end station is physically changed to a different mac address. the last source address (lsa) register (in the port attribute registers) of a port known to be connected to a single station can be programmed with the node id (48-bit mac address) of the dte. if the lsa is not programmed after power up it will be overwritten by the source address of the first packet received, and generate an interrupt if enabled. tp ports p[4:0] = 2, r[4:0] = 6 d port read/write msb lsb t 6 t7 t5 t4 t3 t2 t1 t0 aui port p[4:0] = 2, r[4:0] = 7 d port read/write msb lsb x a x x x x x x the aui port only uses the most significant bit (a) and all other bits are reserved. software should be designed to write 0s into unused bits. port attribute registers the port attribute registers are accessed in the same fashion as the repeater, status or control registers by writing the appropriate port number and register num- ber into the c port. tp port number zero is accessed by writing 0001 0000, tp port number one by writing 00010001 and so on. the aui port attributes are ac- cessed by writing 00011111 to the c port. except for the last source address (lsa) register, all other registers are 4 bytes and read only. the (lsa) reg- ister is 6 bytes long and its contents can be written and read. once the c port is programmed with a valid port (bank) and register (attribute) number, the corresponding at- tribute is transferred to a holding register upon reading the first byte. subsequent accesses to the d port read the value in a least significant to most significant byte or- der. when reading, once the last byte is read, the attrib- ute value is re-transferred to the holding register and the sequence can be restarted. when writing the lsa regis- ter, if the sequence is aborted prior to the sixth consecu- tive write cycle, the internally stored register value is not updated. the sequence (read or write) may be aborted and restarted by programming the c port.
amd p r e l i m i n a r y 1 7 am79c987 note that the contents of all attribute registers are main- tained during an external reset. these attributes and their definitions comply with the ieee 802.3k layer management for 10 mbyte/s baseband repeaters repeater management standard. a brief summary of attribute description is included here for reference only. for detailed description, refer to the ieee 802.3k document. readable frames p[4:0] = 16C23, 31 , r[4:0] = 0 byte 0 byte 1 byte 2 byte 3 bit 7 bit 31 bit 0 bit 24 msb lsb d port read readable frames is a read-only attribute that counts the number of valid frames detected by the port. valid frames are from 64 bytes to 1518 bytes in length, have a valid frame crc and are received without a collision. this attribute is a 32-bit counter with a minimum rollover time of 80 hours. readable octets p[4:0] = 16C23, 31, r[4:0] = 1 byte 0 byte 1 byte 2 byte 3 bit 7 bit 31 bit 0 bit 24 msb lsb d port read readable octets is a read-only attribute that counts the number of octets received on each port. this num- ber is determined by adding the frame length to this reg- ister at the completion of every valid frame. this attribute is a 32-bit counter with a minimum rollover time of 58 minutes. frame check sequence (fcs) errors p[4:0] = 16C23, 31 , r[4:0] = 2 byte 0 byte 1 byte 2 byte 3 bit 7 bit 31 bit 0 bit 24 msb lsb d port read frame check sequence errors is a read-only attribute that counts the number of frames detected on each port with an invalid frame check sequence. this counter is in- cremented on each frame of valid length (64 bytes to 1518 bytes) that does not suffer a collision during the frame. this counter is incremented on each invalid frame, however it is not incremented for frames with both framing errors and frame check sequence errors. this attribute is a 32-bit counter with a minimum rollover time of 80 hours. alignment errors p[4:0] = 16C23, 31, r[4:0] = 3 byte 0 byte 1 byte 2 byte 3 bit 7 bit 31 bit 0 bit 24 msb lsb d port read alignment errors is a read-only attribute that counts the number of frames detected on each port with an fcs error and a framing error. this counter is incremented on each frame of valid length (64 bytes to 1518 bytes) that does not suffer a collision during the frame. frames that have both framing errors and fcs errors are counted by this attribute, but not by the frame check sequence errors attribute. this attribute is a 32-bit counter with a minimum rollover time of 80 hours.
amd p r e l i m i n a r y 1 8 am79c987 frames too long p[4:0] = 16C23, 31, r[4:0] = 4 byte 0 byte 1 byte 2 byte 3 bit 7 bit 31 bit 0 bit 24 msb lsb d port read frames too long is a read-only attribute that counts the number of frames that exceed the maximum valid packet length of 1518 bytes. this attribute is a 32-bit counter with a minimum rollover time of 61 days. short events p[4:0] = 16C23, 31, r[4:0] = 5 byte 0 byte 1 byte 2 byte 3 bit 7 bit 31 bit 0 bit 24 msb lsb d port read short events is a read-only attribute that counts the number of instances where activity is detected with a du- ration less than the shorteventmaxtime (74C82-bit times). this attribute is a 32-bit counter with a minimum rollover time of 16 hours. runts p[4:0] = 16C23, 31, r[4:0] = 6 byte 0 byte 1 byte 2 byte 3 bit 7 bit 31 bit 0 bit 24 msb lsb d port read runts is a read-only attribute that counts the number of instances where activity is detected with a duration greater than the shorteventmaxtime (74C82-bit times), but less than the minimum valid frame time (512-bit times, or 64 bytes). this attribute is a 32-bit counter with a minimum rollover time of 16 hours. note: runts usually indicate collision fragments, a nor- mal network event. in certain situation associated with large diameter networks a percentage of runts may ex- ceed validpacketmintime. collisions p[4:0] = 16C23, 31, r[4:0] = 7 byte 0 byte 1 byte 2 byte 3 bit 7 bit 31 bit 0 bit 24 msb lsb d port read collisions is a read-only attribute that counts the num- ber of instances where a carrier is detected on the port, and a collision is detected. this attribute is a 32-bit counter with a minimum rollover time of 16 hours. late events p[4:0] = 16C23, 31, r[4:0] = 8 byte 0 byte 1 byte 2 byte 3 bit 7 bit 31 bit 0 bit 24 msb lsb d port read late events is a read-only attribute that counts the number of instances where a collision is detected after the lateeventthreshold (480C565-bit times) in the frame. this event will be counted both by the late events attribute, as well as the collisions attribute. this attribute is a 32-bit counter with a minimum rollover time of 81 hours. very long events p[4:0] = 16C23, 31, r[4:0] = 9 byte 0 byte 1 byte 2 byte 3 bit 7 bit 31 bit 0 bit 24 msb lsb d port read very long events is a read-only attribute that counts the number of times the transmitter is active in excess of the mau jabber lockup protection (mjlp) timer (4 ms C 7.5 ms). this attribute is a 32-bit counter with a mini- mum rollover time of 198 days.
amd p r e l i m i n a r y 1 9 am79c987 data rate mismatches p[4:0] = 16C23, 31, r[4:0] = 10 byte 0 byte 1 byte 2 byte 3 bit 7 bit 31 bit 0 bit 24 msb lsb d port read data rate mismatches is a read-only attribute that counts the number of occurrences where the frequency, or data rate of the incoming signal is detectably different from the local transmit frequency. the attribute is a 32-bit counter that is incremented on each such event. note that the rate at which the data rate mismatches attribute will increment, will depend on the magnitude of the difference between the received signal clock and the local transmit frequency. auto partitions p[4:0] = 16C23, 31, r[4:0] = 11 byte 0 byte 1 byte 2 byte 3 bit 7 bit 31 bit 0 bit 24 msb lsb d port read auto partitions is a read-only attribute that counts the number of instances where the repeater has partitioned this port from the network. this attribute is a 32-bit counter that is incremented on each such event. the ap- proximate minimum time between counter roll-overs is 20 days. source address changes p[4:0] = 16C23, 31, r[4:0] = 12 byte 0 byte 1 byte 2 byte 3 bit 7 bit 31 bit 0 bit 24 msb lsb d port read source address changes is a read-only attribute that counts the number of times the source address field of valid frames received on a port changes. this attribute is a 32-bit counter with a minimum rollover of 81 hours. note: this may indicate whether a port is connected to a single dte or another multi-user segment. last source address (lsa) p[4:0] = 16C23, 31, r[4:0] = 14 byte 0 byte 1 byte 2 byte 3 byte 4 byte 5 bit 7 bit 31 bit 0 bit 24 msb lsb d port read/write last source address is a read/write attribute that saves the value of the source address field of the last valid frame it received. this attribute is a 6-byte field. this 6-byte register may be read or written. this feature allows the software to preset this attribute to the known node id, for a single node segment. a change in the contents of this register would then signal an anomaly. this will cause the source address changes attribute to increment. furthermore, setting the respective tp/aui port source address change interrupt enable bit (in the port control registers), can be used to generate a hard- ware interrupt to signal the software to automatically disable this port.
amd p r e l i m i n a r y 20 am79c987 systems applications typical system interface the block diagram on this page shows a typical system interface. a fully managed multiport repeater can be easily built by interfacing the himib chip with the imr+ chip (am79c981). the himib device interfaces with all common microprocessor system busses with a mini- mum of external logic. note that additional buffering of dat and jam are required for most applications. for more information, refer to the amd ieee 802.3 re- peater technical manual. 17306b-5 himib imr+ crs str si so sclk crs str si so sclk req dat jam ack col rst ck address decode cs c/ d data buffer rd wr rdy host system bus expansion bus d7C0 int x1 figure 2. himib device application example
amd p r e l i m i n a r y 21 am79c987 absolute maximum ratings storage temperature C65 c to +150 c . . . . . . . . . . . ambient temperature under bias 0 c to +70 c . . . . . . . . . . . . . . . . . . . . . . suppl y voltage C0.3 v to +6.0 v . . . . . . . . . . . . . . . . stresses above those listed under absolute maximum rat- ings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maxi- mum ratings for extended periods may affect device reliability. operating ranges commercial (c) devices case temperature (t a ) 0 c to +70 c . . . . . . . . . . . . supply voltages (v dd ) 5 v 5 % . . . . . . . . . . . . . . . . . all inputs within the range v d d + 0.5 v v in v ss C0.5 v . . . . . . . . . . operating ranges define those limits between which the func- tionality of the device is guaranteed. dc characteristics symbol parameter description tes t condition min max unit v il input low voltage v ss = 0.0 v C0.5 0.8 v v ih input high voltage 2.0 0.5 +v dd v v ol output low voltag e i ol = 4.0 ma 0.4 v v oh output high voltage i oh = C0.4 ma 2.4 v v olod open drain output low voltage i olod = 12 ma 0.4 v i il input leakage current 0 < v in and v in < v dd +0.5 v 1 0 m a v ilx ck input low voltage v ss = 0.0 v C0.5 1.0 v v ihx ck input high voltage v ss = 0.0 v 3.8 0.5 +v dd v i ilx ck input low current v in = v ss 10 m a i ihx ck input high current v in = v dd 10 m a i dd power supply current f ck = 20 mhz 40 ma
amd p r e l i m i n a r y 22 am79c987 switching characteristics clock and reset timing symbol description test condition min max unit t ck clock period 49.995 50.005 ns t ckh clock high 20 30 ns t ckl clock low 20 30 ns t ckr clock rise time 10 ns t ckf clock fall time 10 ns t rst reset pulse width (note 1) 4 u s t rsts reset input setup time with respect to ck (note 1) 15 ns t rsth reset input hold time with respect to c k (note 1) 0 n s expansion port symbol description test condition min max unit t djset dat/jam setup time 10 ns t djhold dat/jam hold time 9 n s t caset col / ack setup time 5 n s t cahld col / ack hold time 9 n s management port symbol description test condition min max unit t sckd sclk clock delay with respect to ck 9 4 5 ns t sckr sclk rise time with respect to ck c l = 50 pf 10 ns t sckf sclk fall time with respect to ck c l = 50 pf 10 ns t sos so input setup time with 10 ns respect to ck rising edge t soh so input hold time with 9 n s respect to ck rising edge t sid si output delay with c l = 50 pf 9 45 ns respect to ck rising edge port activity monitor symbol description test condition min max unit t crsts crs setup time with 10 ns respect to ck rising edge t crsth crs hold time with respec t 5 n s to ck rising edge note: 1. see imr+ data sheet for reset.
amd p r e l i m i n a r y 23 am79c987 switching characteristics (continued) microprocessor interface (mpi) symbol description test condition min max unit t cds c/ d setup time with 10 ns respect to rd / wr falling edge t cdh c/ d hold time with 0 n s respect to rd / wr rising edge t css cs setup time with respect to 10 ns rd / wr falling edge t csh cs hold time with respect to 0 n s rd / wr rising edge t rest rest period between mpi operations 150 ns (time between the earliest cs / rd / wr going high to the next cs / rd / wr going low, whichever is the latest) t rdyd rdy leading edge delay c l = 100 pf 25 ns t rdyh rdy high to rd / wr - 0 n s t dout data out valid to rdy hig h c l = 100 pf 50 ns t dohld data out hold after rd hig h c l = 100 pf 10 45 ns t diset data in setup time wit h 25 ns respect to wr rising edge t dihld data in hold after wr hig h 0 n s
amd p r e l i m i n a r y 24 am79c987 switching test loads c l v threshold sense point i ol i oh 17305b-6 v cc r1 c l device pin 17305b-7 pin name test circuit r1 c l (pf) all outputs and i/o pins except rdy , int a 100 rdy , int b 400 100 test output loads a. normal and three-state outputs b. open-drain outputs ( rdy , int )
amd p r e l i m i n a r y 25 am79c987 switching test loads (continued) v dd 500 w device pin 500 w 17305b-8 c. for data out (d7C0) hold only
amd p r e l i m i n a r y 2 6 am79c987 key to switching waveforms ks000010 must be steady may change from h to l may change from l to h does not apply dont care, any change permitted will be steady will be changing from h to l will be changing from l to h changing, state unknown center line is high- impedance off state waveform inputs outputs switching waveforms t rsth t rsts t rst t ckr t ckf t ck t ckh t ckl ck rst 3.8 v 1 v 17305b-9 0.8 2.0 clock and reset timing t djset 17305b-10 t cahld t caset t djhold t caset ck ack col dat jam expansion port timing
amd p r e l i m i n a r y 27 am79c987 switching waveforms 17305b-11 t sckd ck sclk si t sckd t sckf t sckr t sid t sid t sos t soh so management port timing 17305b-12 ck crs t crsts t crsth port activity timing
amd p r e l i m i n a r y 2 8 am79c987 switching waveforms t css c/ d t cdh t csh t rdyd t rdyh 17305b-13 t dout t dohld t diset t dihld cs rd, wr rdy d7C0 d7C0 read data write data t cds t rest t rest bus interface timing note: refer to amds ieee 802.3 repeater technical manual (pid #17314a) for more detailed access timing.
2 9 am79c987 imr+/himib security features appendix a the am79c981 integrated multiport repeater plus (imr+) and the am79c987 hardware implemented management information base (himib) ethernet re- peater chip-set is capable of providing physical network security features. amd will only make these features available to customers who are under an imr+/himib security non disclosure agreement (nda). a description of the security feature is summarized below. for more information, contact your local amd sales office to gen- erate an imr+/himib security nda. security features summary the himib incorporates a feature to allow the destina- tion address (da) field of a received packet to be com- pared with the known mac address connected to each port. the mac address for each port is contained in the himib last source address (lsa) register, which can be programmed by the user or it will be learnt by the himib device. on receipt of a packet on one port, all other ports have the contents of the lsa register com- pared with the da field of the received frame. if there is a match on any port, the frame is repeated to that port normally. for those ports which have the security fea- ture enabled and do not have a da/lsa match, the repeated bit stream of the packet will be corrupted (fre- quently termed eavesdrop protection), and the port will transmit an alternating pattern of 1 and 0 following the 18th (approximate) bit of the source address field. this feature can be enabled/disabled on a port by port basis using a mask located in the himib port control regis- ters. any port with the security feature disabled (using the field in the port controls registers) will repeat the packet normally. note that multicast and broadcast packets are transmitted to all ports unmodified, regard- less of the enable/disable state of the security function. ports that are connected to single stations can be se- cured by enabling the eavesdrop protection function and enabling the last source address change inter- rupt. this prevents unauthorized eavesdropping by sta- tions on the lan who are not directly addressed by the sourcing node, hence the learning of valid source ad- dresses and snooping on data is virtually impossible. in addition, this allows the management software to de- tect and possibly disable the port in real time if the himib indicates via the hardware interrupt line that the source address has changed.
trademarks copyright ?1998 advanced micro devices, inc. all rights reserved. amd, the amd logo, and combinations thereof are trademarks of advanced micro devices, inc. am186, am386, am486, am29000, b imr, eimr, eimr+, gigaphy, himib, ilacc, imr, imr+, imr2, isa-hub, mace, magic packet, pcnet, pcnet- fast , pcnet- fast +, pcnet-mobile, qfex, qfexr, quasi , quest, quiet, taxichip, tpex, and tpex plus are trademarks of advanced micro devices, inc. microsoft is a registered trademark of microsoft corporation. product names used in this publication are for identi?ation purposes only and may be trademarks of their respective companies.

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